This invention pertains to high-speed serial interfaces, and, more particularly, to an apparatus and method for injecting controlled amounts and frequencies of timing jitter into the transmit data path of a serial data interface to allow for the convenient testing of jitter tolerance.
In serial interfaces, several parameters of the transmitter and receiver influence the capability of the serial data link to provide data with a very low number of errors over time. This description of the number of errors per number of data bits transferred is known as the “BER” or Bit Error Rate. One of these parameters is known as “receiver jitter tolerance”. In high-speed electronic data systems, the parameter “jitter” or “timing jitter” refers to errors in the placement of a data or clock edge compared to its ideal location. The error can be random in nature or deterministic (having a bounded amplitude). The type of jitter depends on the sources of the jitter in the electronic system. Electronic thermal noise, circuit timing dependence on supply voltage noise, and electromagnetic coupling are some of the sources of this jitter. In general, a system will have a mixture of jitter components in its signals. The receiver jitter tolerance parameter describes how well a receiver can extract data with a low error rate from a digital data stream containing jitter.
Measuring the receiver jitter tolerance has been one of the more demanding measurements due to the equipment required to produce a data stream with known amounts and frequencies of jitter. The equipment needed to generate this jittered data must have higher performance capability than the data link being tested. The BAUD rate or frequency of the data being transferred is increasing rapidly over time to provide faster data operations. The evolution of serial data interfaces in computers is an example of this trend. This increase in operating speed requires higher performance, more advanced equipment to perform these tests. The equipment currently available for such testing is quite expensive and the availability sometimes lags the need for testing the data link. It is also desirable to test the receiver jitter tolerance when the high-speed serial interface is connected into an actual system such as computer or other data equipment. This is difficult to accomplish and prone to errors when using the present jittered data generation equipment such as serial data pattern generators.
Present transmitters for high-speed serial data interfaces do not have the means for providing known amounts and frequencies of jitter for receiver jitter tolerance testing. Some transmitters, such as those with SATA (Serial ATA, wherein “ATA” stands for Advanced Technology Attachment) interfaces have the means for modulating the transmit data stream with a 30 KHz 0% to −0.5% modulation, as is called out in the SATA specification for SSC (Spread Spectrum Clocking) transmission.
Referring now to FIG. 1, a block diagram of a prior art transmission path 10 is shown. An initial timing reference or Base Frequency Clock signal 14 is provided by an internal oscillator 12. The frequency of the clock signal 14 is determined by either a quartz crystal or ceramic resonator or alternately sourced by a reference clock available from the system. This base frequency clock signal 14 is increased in frequency consistent with the data transmission rate of the serial interface in the transmit timing generator 16. In the case of SSC transmission, clock signal 18 is additionally modulated typically at 30 KHz in the transmit timing generation block 16 in order to frequency modulate the data stream to help reduce EMI emissions. This modulated high frequency clock signal 18 is the timing source for the serializer block 13 that converts the parallel data stream 11 into a serial data stream 15 at the data rate determined by clock signal 18. This Serial Transmit Data signal 15 is buffered by a transmit buffer block 17 that provides the specific amplitude and output impedance as is required by a particular interface. In high-speed serial interfaces such as SATA interfaces, the final output signal 19 is differential.
Referring now to FIG. 2, a more detailed block diagram shows a possible prior art implementation 20 of the transmit timing generation block 16 shown in FIG. 1. The clock signal input 22 is input into a high frequency clock generator 24. The output 26 of the clock generator 24 is input into a clock modulator block 28, which provides the modulated clock output signal 23. A modulator command block 27 such as an SSC modulation command provides an output 25 coupled to the clock modulator block 28.
Referring now to FIG. 3, another prior art embodiment 30 of the transmit timing generator 16 of FIG. 1 is shown. Timing generator 30 includes a DLL (Delay Locked Loop) 34 for increasing the frequency of the base frequency clock signal 32 to a frequency consistent with the desired data rate. A clock modulator circuit 38, commanded by a modulation command block 37 modulates the clock signal 36 from the DLL at a 30 KHz rate to provide the SSC modulated high frequency clock output signal 33.
Referring now to FIG. 4, the detailed block diagram shows yet another prior art embodiment 40 of the transmit timing generation block 16 shown in FIG. 1. The detailed block diagram of FIG. 4 shows a similar topology except that the initial frequency multiplication provided by the DLL 34 previously shown in FIG. 3 is now provided by a PLL (Phase Locked Loop) 44.
Referring now to FIG. 5, the detailed block diagram shows an alternative prior art embodiment for the transmit timing generation block 16 shown in FIG. 1. Timing generation block 50 contains a modulated PLL 54 that provides both the frequency multiplication as well as the SSC modulation via modulation command block 58. Typically this can be accomplished by incorporating time varying modifications to the feedback path of the PLL 54.
Referring now to FIG. 6, the detailed block diagram shows yet another prior art alternative embodiment for the transmit timing generation block 16 shown in FIG. 1. Timing generation block 60 contains a modulated DLL 64 that provides both the frequency multiplication as well as the SSC modulation via modulation command block 68. Typically this can be accomplished by incorporating time varying modifications to the delay paths in the DLL 64 structure.
None of the prior art transmit timing generation blocks shown in FIGS. 1–6 has the ability to provide the high-speed jitter testing required by high-speed serial interfaces. Present test equipment for providing the function is extremely expensive, can be hard to obtain, and is difficult to use within operating systems. Lower cost solutions exist although the general prior art method of disturbing the data stream and using the coupled receiver to function as a limiting amplifier that is error prone requires an iterative adjustment and measuring process to get the level desired.
What is desired, therefore, is a method and apparatus for providing convenient high-speed jitter testing that does not have the performance limitations of the lower-cost prior art solutions or the expense and limitations of existing test equipment.